Are you RoHS Compliant?
The impact that RoHS will have on engineering designs and product deployment could include:
- RoHS may require a requalification of a design using the RoHS compliant parts
- A design may have to be re-engineered to support the RoHS compliant parts
- The different chemical makeup of RoHS parts may require an additional “learning curve” for PCB assembly houses to re-tool soldering processes
Additional links on RoHS:
Moving to DDR-SDRAM
If you are an experiened engineering using either asynchonous SRAM style memory or standard Single Data-Rate SDRAM memories, don't take the design challenges of DDR-SDRAM lightly.
DDR-SDRAM provides theoretical bandwiths of upto 3.2GB/s using a 200MHz double-edge triggered memory module or discrete device. DDR-SDRAM also provides timing margins as tight as 200pS!
FLE has collected a series of insightful third-party guides for assisting engineers designing with, or beginning to design with, DDR-SDRAM memory interfaces.
We strongly recommend that anyone attempting to design a DDR-SDRAM memory interface should gain a complete understanding of all areas discussed in these guides.
DDR System Design Considerations
This paper, written by Micron, provides a terrific overview of the SSTL-2 technology, DDR memory bus topologies, terminiation techniques, voltage margin requirements, and layout techniques.
› DDR System Design Considerations (PDF)
This paper, written by Fairchild Semiconductor, details informatin on the voltage-reference requirement for DDR-SDRAM and how to provide and implement a stable VREF.
› DDR Signaling (PDF)
DDR Top 10 Mistakes
This paper, written by Micron, gives an outstanding overview of the “Top-10” common mistakes when implementing a DDR-SDRAM memory system. Great reading for implementing ANY memory technology.
› DDR Top 10 Mistakes (PDF)
Contact FLE for help with your DDR-SDRAM Design