Details
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- An example VESA timing chart to help determine the horizontal/vertical/clock video timing.
- For full specifications, a trial version, or additional support, contact Finger Lakes Engineering.
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IP Core
Viper Video Display
Part of the Viper Video Technology Suite
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Purchase
$5,000/each
The FLE Viper Video Display Core is part of the Finger Lakes Engineering Viper Video technology suite.
The Viper Video Display core is targeting specifically for Microblaze applications seeking to control an external DVI/Analog monitor OR directly drive a TFT/LCD Display.
The Viper Video Display core is a bus-mastering PLB compliant core providing the following key features:
- Upto 1024x768 video at 65MHz system clock rate in a Spartan-Class device
- Upto 1280x1024 video at 80MHz system clock rate in a Virtex or fastest speed Spartan-Class Device
- 16-bit-per-pixel frame buffer video input (RGB565)
- 24-bit-per-pixel interpolated video output (RGB888)
- Configurable timing based on VESA standard timing sheets
- No CPU intervention required during video display operations
- Compliant with the PLB 4.6 and provides internal BusMaster function
- Supported through the FLE FUSION uCLinux system
- Can be used via a stand-along register driven interface
- FLE can customize the core for specific user applications
The block diagram of the Viper Video Display Core
The FLE Viper Video Display core is available as a time-limited trial version for evaluation.