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Full Specifications
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For a trial version, or additional support, contact FLE.

The Lancer core is available as a time-limited trial version for evaluation and has been packaged into a reference design for the Spartan3-700AN Eval Board. Please see the reference designs available under the FUSION pages.

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IP Core

Lancer

I2S Audio Core

Purchase

$1,250/each

The Lancer I2S Audio Core is targeted specifically for Microblaze applications seeking to connect directly to industry standard I2S DAC devices and products mono/stereo audio outputs.

The Lancer provides a configurable slave interface to define buffer lengths and interact with a host/OS driver layer.The Lancer provides a PLB Master interface which is used to transfer audio samples from an external memory and load them into an internal FIFO for transmission to an I2S DAC.

The Lancer utilizes a single sample rate clock which can be generated within the FPGA from a DLL/PLL or provided from an external clock source. In addition, the sample clock can be varied during operation to allow multiple playback sample rates to be achieved. The sample clock is, by design, asynchronous to all other FPGA clocks.

The Lancer core provides the following key features:

Internal/External clock domain synchronization
Supports a variable sample clock from 1MHz to over 60MHz
16-bit mono/stereo sample support
Direct interface to an I2S coded with 16-bit right justified format
No CPU intervention required during playback from an external buffer
Compliant with PLB 4.6 and provides an internal BusMaster function
Supported through the FLE FUSION uCLinux system
Can be used via a stand-along register driven interface
FLE Can customize the core for specific user applications/alternate I2S formats

The block diagram of the Lancer I2S Audio Core

Download the Full Specifications for the Lancer I2S Audio Core.