PLB Microblaze Cores

Finger Lakes Engineering Xilinx Microblaze IP Cores

Finger Lakes Engineering is commiting the following Xilinx IP Cores as part of our Free From FLE program.

These cores are typically used in a variety of customer designs and our FUSION uCLinux implementations. These cores can be used under the conditions of the “F3 License” program. The cores provide useful, but non-propritary, technology to help jumpstart a Microblaze design.

All of these cores are compatible with the PLB 4.6 Bus Interconnect standard and can be used in both Microblaze and PowerPC designs using Xilinx FPGA Technology.

InterruptConverter

This core can take an edge interrupt signal and convert it into a level sensitive interrupt signal. Useful to correct certain IP cores that may allow for “missed interrupts” if an edge occurs during an interrupt clear event.

› Download FLE InterruptConverter
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Power On Reset

Simple core which can generate a controlled internal reset signal for starting logic up without the use of an external reset pin. Useful in starting up DLL/PLLs after device initialization.

› Download FLE Power On Reset
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LCD Controller

The FLE LCD Interface Core allows a 4-bit or 8-bit ASCII-type LCD display to be directly mapped into the memory space of the Microblaze processor. This core greatly simplifies reading and writing command and data cycles to the LCD display.

› Download FLE LCD Controller
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ST Micro Serial Flash Interface Core

The FLE ST-FLASH Core provides a dedicated read/write/erase and page-mode program support for connecting the Microblaze directly to ST 25PXX Serial Flash Memory devices. FLE has used this core with the 8MB (25P64 device) in several instances. A basic driver file is provide which allows RAM-to-FLASH, FLASH-to-RAM, testing, and code execution from within RAM memory

› Download ST Micro Serial Flash Interface Core
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NAND Memory Interface

The FLE NAND Memory provices a direct PLB slave interface supporting a single 8-bit external NAND memory. The core allows assertion of the CL, AL, Read/Write of the 8-bit bus, and monitoring of the ReadyBusy pin.

› Download FLE NAND Memory Interface
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MDIO Master Controller

The MDIO Master Controller allows a simple PLB Slave to provide read/write cycles to an external MDIO device such as an ethernet PHY. This IP Core complements the free Xilinx Ethernet Controller and/or allows the user to easily control multiple MDIO devices.

› Download FLE MDIO Master Controller
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